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dts: riscv: aesc: Add reg-names to machine timer node #90692

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Merged
merged 1 commit into from
May 27, 2025

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@kartben kartben commented May 27, 2025

Commit 42fb906 makes it mandatory to now have reg-names property on the riscv,machine-timer node. This DTS file was somehow missed as part of the refactoring.

Commit 42fb906 makes it mandatory to
now have reg-names property on the riscv,machine-timer node. This DTS
file was somehow missed as part of the refactoring.

Signed-off-by: Benjamin Cabé <[email protected]>
@kartben kartben added the Hotfix Fix for issues blocking development, i.e. CI issues, tests failing in CI, etc. label May 27, 2025
@kartben kartben marked this pull request as ready for review May 27, 2025 19:09
@kartben kartben requested review from aescolar and xingrz May 27, 2025 19:09
@github-actions github-actions bot added area: RISCV RISCV Architecture (32-bit & 64-bit) area: Aesc Silicon Platform size: XS A PR changing only a single line of code labels May 27, 2025
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@kartben kartben merged commit 464a49d into zephyrproject-rtos:main May 27, 2025
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@kartben kartben deleted the elemrv branch May 28, 2025 15:54
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area: Aesc Silicon Platform area: RISCV RISCV Architecture (32-bit & 64-bit) Hotfix Fix for issues blocking development, i.e. CI issues, tests failing in CI, etc. size: XS A PR changing only a single line of code
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6 participants