FPGA series # 代码习惯之if的嵌套

最新推荐文章于 2026-06-24 18:42:20 发布

原创最新推荐文章于 2026-06-24 18:42:20 发布 · 5.1k 阅读

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本文详细探讨了AXI4-Stream接口中信号同步的优化策略，通过拆分逻辑，清晰地展示了如何在复位条件下正确处理信号，避免过多的嵌套if语句，确保信号在不同模块间稳定、高效地传输。

always@(posedge clk) begin
	s_axis_gamma_tready <= m_axis_gamma_tready ;
	if(resetn) begin
		m_axis_gamma_tvalid <= s_axis_gamma_tvalid 	 ;
		m_axis_gamma_tlast  <= s_axis_gamma_tlast	 ;
	if(s_axis_gamma_ruser)	begin
		if(m_axis_gamma_tvalid && m_axis_gamma_tready)
		 m_axis_gamma_tuser <= 1	;
		else
		 m_axis_gamma_tuser <= 0	;
	end
	end
	else
		m_axis_gamma_tvalid <= 0	;
end

改成

always@(posedge clk) begin
	s_axis_gamma_tready <= m_axis_gamma_tready ;
	m_axis_gamma_tlast  <= s_axis_gamma_tlast  ;
end
//m_axis_gamma_tvalid
always@(posedge clk) begin
	if(!resetn)
		m_axis_gamma_tvalid <= 0	;
	else
		m_axis_gamma_tvalid <= s_axis_gamma_tvalid ;
end
//m_axis_gamma_tuser
always@(posedge clk) begin
	if(!resetn)
		m_axis_gamma_tuser <= 0	;
	else if(s_axis_gamma_tuser) begin
			if(m_axis_gamma_tvalid && m_axis_gamma_tready)  //
		 		m_axis_gamma_tuser <= 1	;
			else
		 		m_axis_gamma_tuser <= 0	;
	end
end

①逻辑要清晰，层次要分明，还是这句老话。
②习惯要先看初始化的值，所以先if(!resetn)，而不是if(resetn)
③一个always里面不要写太多if的嵌套。

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