MEI card Spec note

note that this assumes that the board routing has enough margins to allow for the operations of the MEI in the channel
5. In a burst of 8 or 4 can inject errors on every other burst line due to timing limitations.
6. The MEI due to additional trace length and connector may not work on all the slots on the board.
7. It is recommended that you only put 1 MEI in a given channel to avoid signal integrity issues. However on some boards with additional margin and MEI and DIMM in a 2 or 3 DIMM per channel will work (however there are no assurances)..
1..4.2 Functional Operation
3. Inject errors on a command and address combination.
a. Inject errors on a read, write or read and write command at a specified address. Note that one needs to ensure that there is traffic at the desired address.
On address definition the combinations include (note that in the initial release of the MEI the chip ID value will be a default value since it does not change on the platform):
4. The MEI can inject errors periodically for a specified length of time. Note that this feature should be used with caution since you do not want to run the MEI for too long due to heating (otherwise ensure you have sufficient cooling). If you are injecting very few errors for a short time then disarming for a length of time and repeating, that would be the ideal usage to avoid potential overheating.
1.6
The test items listed below is the complete list of hardware and software needed for the use of the MEI
SUT with a way to verify erros are being injected.
2.1
The only additional software that may be needed in the system  under test is one that generate memory traffic.
ii. Connect the USB cable to the MEI header and note that it is color coded for orientaition.
v. Insert the MEI into the DIMM slot of interest. Ensure that if your system is not fully loaded you are following the correct DIMM installation configuration per platform. In some cases due to the MEI height in a system with risers you may need to remove the adjacent riser.
vi. The power connector hangs from the back side of the MEI.
The platform will either
2.1.2 Error injection
The MEI operates by simply either raising or lowering a tate on a line - it cannot anticipate the statet of the line prior... it cannot toggle the state of the line (as that would be too intrusive and could affect timing such that the DDR bus could become corrupt). The 'success count' is a count of the number of times that the MEI has a CA match and then either raises or lowers the state of the data line in an errort to force an error.

In the script line below the MEI is being programmed to raise the state of lane 2 in an attempt to perform a single bit error on lan 2...
lane = xxxxx1xx
Note here that MEI has no idea if lane 2 is high (1) or low(0) when it performs the 'injection' - so if it was to be high when it was programmed to inject a '1' then the error would not be injected as the state on lane 2 would not be altered by MEI. This means that the actual errors reported by the platform will likely be lower than the MEI reported 'success count'.