南大数字逻辑与计算机组成课程实验三加法器与ALU 思路与代码参考

top.v

module top(
  input [3:0] A,
  input [3:0] B,
  input [2:0] ALUctr,
  output reg [3:0] ALUout,
  output reg [3:0] temp,
  output reg less,
  output reg of,zf,cf
);
reg [3:0] xb;
always@(*)begin
  ALUout = 4'b0;temp = 4'b0; less = 1'b0; of = 0; zf = 0; cf = 0; xb = 4'd0; // 初始化
  casez(ALUctr)
    3'b00z:begin // add or sub
      xb = B ^ {
   
    {
   
   4{
   
   ALUctr[0]}} };  // 根据最后一位确定加减法 加：000 减：001 减法则取反
      {
   
   cf,ALUout} = xb + A + {
   
   3'b0,ALUctr[0]};
	    of = (A[3] == xb[3]) && (ALUout[3] != A[3]);
	    zf = ~(|ALUout);
    end
    3'b011:begin // and
      ALUout = A & B;
    end
    3'b100:begin // or
      ALUout = A | B;