TLC5620 DAC芯片驅動設計

最新推荐文章于 2024-11-11 21:04:16 发布

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本内容遵循CC 4.0 BY-SA版权协议

本文档描述了TLC5620 DAC芯片的驱动设计，通过Verilog代码展示了如何使用串行接口时钟CLK、数据输入DATA、加载控制LOAD和加载DAC信号。代码中包含了一个计数器模块和线性序列机模块，用于根据控制字ctrlword逐位传输数据到DAC，并在传输结束后设置done标志。

// {A1,A0}為A,B,C,D四個通道選擇
// RNG為0或1

module TLC5620_DAC(clk,rst,ctrlword,CLK,DATA,LOAD,LDAC,done);
input clk; // 50M Hz
input rst;
input [10:0] ctrlword;  // {A1,A0,RNG,DATA[7:0]}
output CLK; // 串行接口時鐘
output DATA; // 串行接口數據輸入
output LOAD; // 串行數據加載控制
output LDAC;  // 加載DAC
output done; // 傳輸結束標誌

reg CLK;
reg DATA;
reg LOAD;
reg LDAC;
reg en;
reg done;
reg [9:0] cnt;

//========================================================
// 計數器
//========================================================

always@(posedge clk or negedge rst)
begin
if(!rst) cnt <= 10'd0;
else if(en)
begin
if(cnt == 10'd820) cnt <= 10'd0;
else cnt <= cnt + 10'd1;
end
else cnt <= cnt;
end

//========================================================
// 線性序列機
//========================================================

always@(posedge clk or negedge rst)
begin
if(!rst)
begin
CLK <= 1'b0;
DATA <= 1'b0;
LOAD <= 1'b0;
LDAC <= 1'b0;
en <= 1'b0;
done <= 1'b0;
end
else
begin
case(cnt)
0:begin
CLK <= 1'b0;
DATA <= 1'b0;
LOAD <= 1'b1;
LDAC <= 1'b0;
en <= 1'b1;
done <= 1'b0;
end
10:begin
CLK <= 1'b1;
DATA <= ctrlword[10];
end
40:begin
CLK <= 1'b0;
end
70:begin
CLK <= 1'b1;
DATA <= ctrlword[9];
end
100:begin
CLK <= 1'b0;
end
130:begin
CLK <= 1'b1;
DATA <= ctrlword[8];
end
160:begin
CLK <= 1'b0;
end
190:begin
CLK <= 1'b1;
DATA <= ctrlword[7];
end
220:begin
CLK <= 1'b0;
end
250:begin
CLK <= 1'b1;
DATA <= ctrlword[6];
end
280:begin
CLK <= 1'b0;
end
310:begin
CLK <= 1'b1;
DATA <= ctrlword[5];
end
340:begin
CLK <= 1'b0;
end
370:begin
CLK <= 1'b1;
   DATA <= ctrlword[4];
end
400:begin
CLK <= 1'b0;
end
430:begin
CLK <= 1'b1;
DATA <= ctrlword[3];
end
460:begin
CLK <= 1'b0;
end
490:begin
CLK <= 1'b1;
DATA <= ctrlword[2];
end
520:begin
CLK <= 1'b0;
end
550:begin
CLK <= 1'b1;
DATA <= ctrlword[1];
end
580:begin
CLK <= 1'b0;
   end
610:begin
CLK <= 1'b1;
   DATA <= ctrlword[0];
end
640:begin
CLK <= 1'b0;
end
670:begin
LOAD <= 1'b0;
end
800:begin
LOAD <= 1'b1;
end
819:begin
en <= 1'b0;
end
820:begin
en <= 1'b0;
done <= 1'b1;
end
default:;
endcase
end
end

//====================================================

endmodule

`timescale 1ns/100ps

module TLC5620_DAC_test1;
reg clk,rst;
reg [10:0] ctrlword;
wire CLK,DATA,LOAD,LDAC,done;

TLC5620_DAC TLC5620_DAC(
.clk(clk),
.rst(rst),
.ctrlword(ctrlword),
.CLK(CLK),
.DATA(DATA),
.LOAD(LOAD),
.LDAC(LDAC),
.done(done)
);

initial
begin
clk=1'b1;
forever #20 clk = ~clk;
end

initial
begin
#0
rst = 1'b0;
#1
rst = 1'b1; ctrlword = {2'b00,1'b0,8'd55};
#50000
$stop;
#10
$finish;
end

endmodule