DDS直接數字頻率合成器

原创已于 2022-05-19 02:32:19 修改 · 182 阅读

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于 2021-02-25 00:22:59 首次发布

本文介绍了一个FPGA实现的DDS模块，通过输入的频率控制字和相位控制字，产生相应的输出数据。DDS核心包括相位累加器、相位平移和ROM查表，用于生成所需频率的信号。在测试模块中，设置了不同参数来验证DDS的功能。

module DDS(
clk, //50M Hz
rst_n,
en, //使能
F_word, //頻率控制字
P_word, //相位控制字
DA_data //輸出數據
);
input clk;
input rst_n;
input en;
input [31:0] F_word;
input [11:0] P_word;
output [11:0] DA_data;
reg [31:0] fre_acc;
reg [31:0] F_word_reg;
reg [11:0] P_word_reg;
reg [11:0] rom_addr;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
F_word_reg <= 32'd0;
else
F_word_reg <= F_word;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
P_word_reg <= 12'd0;
else
P_word_reg <= P_word;
end
always@(posedge clk or negedge rst_n) //相位累加器
begin
if(!rst_n)
fre_acc <= 32'd0;
else if(en)
fre_acc <= fre_acc + F_word_reg;
else
fre_acc <= 32'd0;
end
always@(posedge clk or negedge rst_n) //相位平移
begin
if(!rst_n)
rom_addr <= 12'd0;
else if(en)
rom_addr <= fre_acc[31:20] + P_word_reg;
else
rom_addr <= 12'd0;
end
rom rom( //4096*12
.address(rom_addr),
.clock(clk),
.q(DA_data)
);
endmodule

`timescale 1ns/100ps

module DDS_test1;
reg clk;
reg en;
reg rst_n;
reg [31:0] F_word;
reg [11:0] P_word;
wire [11:0] DA_data;

DDS DDS(
.clk(clk),
.en(en),
.rst_n(rst_n),
.F_word(F_word),
.P_word(P_word),
.DA_data(DA_data)
);

initial
begin
clk = 1'b0;
forever #20 clk = ~clk;
end

initial
begin
#0
rst_n = 1'b0;
F_word = 32'd20000000;  //F_word=2^N*(Fout/Fclk), Fout為欲輸出頻率
P_word = 12'd1024;   //P_word=平移角度/(2*PI/2^M), 取平移角度為PI/2
#40
rst_n = 1'b1;
en = 1'b1;
#5000000
#10 $stop;
#10 $finish;
end

endmodule

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#fpga开发