state fsm demo

原创已于 2023-12-26 22:15:06 修改 · 460 阅读

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GEO检测

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数字电路设计

于 2023-12-26 22:07:36 首次发布

本文详细描述了一个使用Verilog编写的逻辑状态机，通过输入向量和状态寄存器控制state的转换，包括IDLE、RUN和END三种状态。状态机在时钟上升沿触发状态更新。

logic state_is_idle;
logic state_is_run;
logic state_is_end;

localparam IDLE = 3'b001;
localparam RUN  = 3'b010;
localparam END  = 3'b100;

reg [2:0] state;
reg [2:0] next_state;
assign {state_is_end, state_is_run, state_is_idle};

wire [1:0] input_vector;
assign input_vector = {the_out, the_enable};

always_comb begin
    casex ({state, input_vector})
        {IDLE, 2'bX1}: next_state = RUN;
        {RUN,  2'b1X}: next_state = END;
        {END,  2'bXX}: next_state = IDLE;
        default: next_state = state;
    endcase
end
    
always_ff@(posedge clk) begin
    if(!rst_n) begin
        state <= IDLE;
    end else begin
        state <= next_state;
    end
end

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#设计模式