Skip to content
View RIOSLaboratory's full-sized avatar
79 followers · 0 following

Achievements

Achievement: Starstruck

Achievements

Achievement: Starstruck

Block or report RIOSLaboratory

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
RIOSLaboratory/README.md

image

RISC-V International Open Source Laborator

In November 2019, the RISC-V International Open Source Laboratory (RIOS Lab) was officially unveiled. Under the leadership of 2017 A.M. Turing Award winner Prof. David A. Patterson and operational support from TBSI, RIOS Lab will conduct cutting-edge research in RISC-V hardware and software technology.

image

Patterson first proposed the Reduced Instruction Set Computer (RISC), an open and free instruction set architecture enabling a new era of processor innovation through open standard collaboration. Released in 2010, the latest Fifth Generation RISC has gained worldwide attention.

image

The name for the lab RIOS is also inspired by the Spanish word for “rivers.” It symbolizes the flow of information from many sources, coming together to create a whole that is greater than the sum of its parts.

image

Associate Members

image

Popular repositories Loading

  1. OpenRPDK28 OpenRPDK28 Public

    Open source process design kit for 28nm open process

    65 10

  2. OpenXRAM OpenXRAM Public

    sram/rram/mram.. compiler

    Verilog 42 6

  3. OpenSTDCell28 OpenSTDCell28 Public

    Open stadard cell library for open 28nm process

    10 2

  4. Open3DFlow Open3DFlow Public

    Forked from chenweiphd/Open3DFlow

    Jupyter Notebook 8

  5. CyberRio-V1.0 CyberRio-V1.0 Public

    A small RISC-V core written in synthesizable Verilog, with the majority of the Verilog code implementation done using GPT-4, that supports the RV32I unprivileged ISA and parts of the privileged ISA…

    Verilog 5 1

  6. Open3DRISCV Open3DRISCV Public

    Forked from chenweiphd/Open3DRISCV

    4