With ISS as one abstraction level option in Wireguard-FPGA sim TB, we are looking for it to be timing-aware. And so in a structured, plug-and-play way.

This mean that, while it does not need to be fully cycle-accurate, but only "close enough", the ISS should also allow easy swaps and user-accessible adjustments of its timing model. This article presents what is currently available. What seems to be missing is:

• ability to specify clock frequency
• standardized method for customizing timing parameters to any given RISC-V CPU, possibly with a worked out library of a few popular options*
• timing model of caches, possibly with following two options:

• Statistical -- Random spread from 0 to a given n, where n can be set by user
• Functional -- Configurable for size of lines, number of ways and number of sets

(*)

1. Ibex timing model.

2. PicoRV32 timing model should use the following settings:

• 5 cycles for Load and Store
• 4 cycles for everything else
  That's for on-chip TCM as it currently does not have any Caching option.

3. eduBOS5 info card shows that in its standard "2-stage" config, the core consumes:

• 3 cycles for Load and Store
• 2 cycles for everything else

eduBOS5 "3-stage" pipeline option adds 1 cycle to everything. It in return allows faster clock.