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Pull requests: chipsalliance/caliptra-rtl

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Pull requests list

[VAL] Add exception on hready assertion for addr decode miss (error case)
#1082 opened Oct 10, 2025 by calebofearth Loading…
Add CALIPTRA_MODE_SUBSYSTEM to config_defines.svh
#1063 opened Sep 30, 2025 by clayton8 Loading…
[DOC] Remove 'definition of done' from integration requirements
#1061 opened Sep 29, 2025 by calebofearth Loading…
@ericeilertson
SHA3 coverage
#1060 opened Sep 26, 2025 by marnovandermaas Loading…
7
Fix state_endianness description sha3_reg.rdl
#1009 opened Aug 28, 2025 by mtimkovich Loading…
7
[RTL] Fix DMA AES FSM going into DONE before DMA FSM with 1 DWORD
#991 opened Aug 26, 2025 by nileshbpat • Draft
[RTL, VAL] DMA AES GCM & AES NON GCM
#943 opened Aug 5, 2025 by nileshbpat Loading…
12
[DOC] RDL: list all python requirements
#939 opened Aug 1, 2025 by marnovandermaas Loading…
Brought out reset signals at the interface for necessary reset handline
#922 opened Jul 15, 2025 by jchanga Loading…
2
[VAL] Add DMA tests for missing coverage
#918 opened Jul 7, 2025 by anjpar Loading…
[UVM] Add AXI sub sequences to soc_ifc environment
#831 opened Mar 18, 2025 by upadhyayulakiran Loading…
3
Auto-generation of regression yaml files for Calitpra_top regression runs.
#755 opened Feb 25, 2025 by anjpar Loading…
DCLS integration Future
#737 opened Feb 18, 2025 by kgugala Loading…
Add coverage report
#587 opened Sep 10, 2024 by kiryk Loading…
2
Add test for JTAG during uC reset
#554 opened Jul 4, 2024 by robertszczepanski Loading…
Patch 1.0 RTL with Lint Fixes enhancement New feature or request
#518 opened May 17, 2024 by calebofearth Loading…
@calebofearth
9
Fix PC setup after waking from clock gating in Verilator Future
#380 opened Jan 16, 2024 by robertszczepanski Loading…
12
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