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1. systolic-NN-accelerator-on-FPGA-with-metrics systolic-NN-accelerator-on-FPGA-with-metrics Public

   Forked from ANIL-RONGALA/systolic-NN-accelerator-on-FPGA-with-metrics

   Designing and implementing a scalable systolic-array neural-network accelerator (4×4 PE array, tile-based mat-mul) in SystemVerilog; verified with a Python golden model and SystemVerilog testbench …

   Verilog 1

2. VAR-CLIP VAR-CLIP Public

   Forked from daixiangzi/VAR-CLIP

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3. bilibili_repository bilibili_repository Public

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4. Booth4_wallace_MULT16_16 Booth4_wallace_MULT16_16 Public

   Forked from lauchinyuan/Booth4_wallace_MULT16_16

   A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction

   Verilog

5. Radix-4_Booth_Multiplier Radix-4_Booth_Multiplier Public

   Forked from BelfortXP/Radix-4_Booth_Multiplier

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6. hardware-multiplier-architectures hardware-multiplier-architectures Public

   Forked from arvkr/hardware-multiplier-architectures

   Verilog implementations of 6 different hardware multiplier architectures

   Verilog