Introduction

Addition of the CY8CPROTO-062-4343W, with support for Counter, I2C, UART, Wi-Fi and BLE in Zephyr. Move existing device support to use the Infineon Hardware Abstraction Layer (HAL), rather than the direct Peripheral Driver Library (PDL) usage. Update of the CY8CKIT-062-BLE and CY8CKIT-062-WIFI-BT boards to the new Infineon SoC/Devicetree.

Problem description

We have customers wishing to use the CY8CPROTO-062-4343W board as an evaluation platform in Zephyr. Additionally, since the CY8CKIT-062* kits were introduced Cypress/Infineon has changed its strategy for its SOC SDK, building as much of our device integration and middleware support on top of the Infineon HAL.

Proposed change

Addition of the CY8CPROTO-062-4343W board, along with implementations for UART, I2C, Counter and Clock Control Drivers for the PSoC 6. Update of the CY8CKIT-062-BLE and CY8CKIT-062-WIFI-BT boards.

Detailed RFC

In this section of the document the target audience is the dev team. Upon
reading this section each engineer should have a rather clear picture of what
needs to be done in order to implement the described feature.

Proposed change (Detailed)

Infineon Hardware Abstraction Layer (HAL)

Using Infineon Hardware Abstraction Layer (HAL) in Zephyr drivers implementation allow us to make integration more scalable (adding new device families in the future) and more robust, since the Infineon HAL is already tested in multiple environments/SDKs.
Integration details

1. The Infineon Hardware Abstraction Layer manages configuration of peripheral pins , it requires the cyhal_gpio_t instances to be provied to init functions. The Pin Control driver (pinctrl_infineon_cat1.c) will have a nonpublic function, which will be used in Infineon CAT1 Zephyr peripheral drivers (*_infineon_cat1.c) to retriever cyhal_gpio_t from pinctrl_soc_pin_t.
2. The Infineon Hardware Abstraction Layer manages peripheral and provides a set of callbacks (which can be registered). Infineon HAL uses Cy_Int_Init (from PDL) to setup drivers' interrupt handlers. The default Zephyr vectors table implementation is not compatible with PDL/CYHAL, because the Zephyr Vector table is located in ROM, and SW ISR Table is not compatible with __ramVectors due to being extended by args _isr_table_entry structure. To allow Infineon Hardware Abstraction Layer to works with interrupts, the following will be done:� - enable CONFIG_DYNAMIC_INTERRUPTS to move SW ISR Table to ram,� - reimplement Cy_Int_Init in soc.c to use Zephyr API irq_connect_dynamic instead Cy_SysInt_SetVector.

Cortex-M0+ support

In the PSoC 6-based integration, the family's Cortex-M0+ will be controlled by a pre-built image, rather than being open to the user. This aligns with our current PSoC 6 strategy. This pre-built image will be acquired from the Infineon MCU SDK via west extensions the user will invoke when creating a PSoC 6-based application. In future revisions of our Zephyr support, including when adding new device families, we will seek to open the Cortex-M0+ for user development.

SOC integration

Folders/files structure to add support PSoC 6 SOC in Zephyr:
zephyr\soc\arm\infineon_cat1
  |--> psoc6
  |        |--> CMakeLists.txt Cmake includes linkers, soc.c,  etc
  |        |--> CMakeLists.psoc6_1.txt* Defines for PSoC 6 1M family
  |        |--> CMakeLists.psoc6_2.txt* Defines for PSoC 6 2M family
  |        |--> CMakeLists.psoc6_3.txt* Defines for PSoC 6 512 family
  |        |--> CMakeLists.psoc6_4.txt* Defines for PSoC 6 256 family
  |        |--> Kconfig.series List of PSoC 6 series (60, 61, 62, 63, 64 )
  |        |--> Kconfig.soc Includes MPNs and CM0p images lists
  |        |--> Kconfig.defconfig.soc.psc6_01* Defines  PSoC 6 MPNs of PSoC 6A-BLE
  |        |--> Kconfig.defconfig.soc.psoc6_02* Defines  PSoC 6 MPNs of PSoC 6A-2M
  |        |--> Kconfig.defconfig.soc.psoc6_03* Defines  PSoC 6 MPNs of PSoC 6A-512
  |        |--> Kconfig.defconfig.soc.psoc6_04* Defines  PSoC 6 MPNs of PSoC 6A-256
  |        |--> Kconfig.defconfig General die options (defines default SYS_CLOCK_HW_CYCLES_PER_SEC and ROM_START_OFFSET)
  |        |--> Kconfig.defconfig.psoc6s1* Base die options for PSoC 6A-BLE (defines NUM_IRQS, etc)
  |        |--> Kconfig.defconfig.psoc6s2* Base die options for PSoC 6A-2M (defines NUM_IRQS, etc)
  |        |--> Kconfig.defconfig.psoc6s3* Base die options for PSoC 6A-512 (defines NUM_IRQS, etc)
  |        |--> Kconfig.defconfig.psoc6s4* Base die options for PSoC 6A-256 (defines NUM_IRQS, etc)
  |        |--> ***.ld linkers scripts for PSoC 6
  |        |--> soc.c/h Initializes the system
  |--> CMakeLists.txt Includes all cmake from psoc6/CMakeLists***
  |--> Kconfig Entry point of Kconfig
  |--> Kconfig.defconfig Entry point of Kconfig.defconfig (includes  other *.defconfig from psoc6)
  |--> Kconfig.soc Entry point of soc (includes  psoc6/Kconfig.series)

Devicetree

The contents of PSoC 6 devicetree can be automatically generated by internal tools that we already use for generating chip specific files from design data. This would simply be an additional file writer for the tool. Once generated they should be placed into the /dts/arm/infineon/ directory to ship with Zephyr.
Proposed the following folders/files structure for PSoC 6 devicetree in Zephyr:

infineon
|--> psoc6
| |--> mpns
|                |--> CY8C6016BZI_F04.dtsi
|                |--> CY8C6036BZI_F04.dtsi
|                |--> CY8C6116BZI_F54.dtsi
|                |--> CY8C6117BZI_F34.dtsi
|                |--> CYS0644ABZI_S2D44.dtsi
|                |--> CY8C6117FDI_F02.dtsi
|                |--> ...
|                |--> CYS0644ABZI_S2D44.dtsi
| |--> psoc6_01
|                |--> psoc6_01.dtsi
|                |--> psoc6_01.104-m-csp-ble.dtsi
|                |--> psoc6_01.116-bga-ble.dtsi
|                |--> psoc6_01.116-bga-usb.dtsi
|                |→ psoc6_01.124-bga.dtsi
|                |-->...
| |--> psoc6_02
|                |--> psoc6_02.dtsi
|                |--> psoc6_02.100-wlcsp.dtsi
|                |--> psoc6_02.124-bga.dtsi
|                |--> psoc6_02.128-tqfp.dtsi
|                |--> psoc6_02.68-qfn.dtsi
| |--> psoc6_03
|                |--> psoc6_03.dtsi
|                |--> psoc6_03.100-tqfp.dtsi
|                |--> psoc6_03.49-wlcsp.dtsi
|                |--> psoc6_03.68-qfn.dtsi
| |--> psoc6_04
|                |--> psoc6_04.dtsi
|                |--> psoc6_04.64-tqfp-epad.dtsi
|                |--> psoc6_04.68-qfn.dtsi
|                |--> psoc6_04.80-tqfp.dtsi

Drivers for this release

Pinctrl
Clock_control
GPIO
Counter
I2C
UART
Wi-Fi
BLE

Binary Assets

Any libraries which contain binary files (e.g Bluetooth chip firmwares, CM0p prebuilt images, etc) will be hosted on Infineon Github repo: http://github.com/infineon/infineon_zephyr_connectivity.git. We will provide instructions for users to install the Infineon Connectivity Zephyr module with the submanifests mechanism.
The steps would be similar to this:

1. Get the Zephyr source code
   west init
2. Add infineon_connectivity.yaml manifest in to zephyr/submanifests folder. The snippet of infineon_connectivity.yaml would be:
   manifest:
   projects:
   - name: infineon_zephyr_connectivity
   url: http://github.com/infineon/infineon_zephyr_connectivity.git
   submodules: true
   revision: main
   path: modules/hal/infineon_connectivity
   groups:
   - hal
3. Update Zephyr modules
   west update

Dependencies

None known.

Tasks

Phase 1 (preparation)

• Update Cypress PSoC 6 SoC to use new hal_infineon\mtb-pdl-cat1
• Remove hal_cypress from Cypress PSoC 6 SoC and add hal_infineon

Phase 2 (develop initial Infineon PSoC 6 SoC)

• Introduce Infineon CAT1/PSoC 6 SoC
• Introduce Infineon CAT1/PSoC 6 Devicetree
• Add Pin Control Driver
• Add Clock Control Driver
• Add GPIO Driver
• Add UART Driver
• Add I2C Driver
• Add Counter Driver
• Add Wi-Fi Driver
• Add CYW43xxx BLE HCI extension Driver

Phase 3 (Add CY8CPROTO-062-4343W board)

• CY8CPROTO-062-4343W board representation using Infineon CAT1/PSoC 6 SoC

Phase 4 (Driver Coverage Expansion to match Cypress PSoC 6 SoC)

• Add HWINFO Driver
• Add SPI Driver

Phase 5 (Exiting board migration to Infineon CAT1/PSoC 6 SoC)

• Update CY8CKIT-062-BLE to new SoC
• Update CY8CKIT-062-WIFI-BT to new SoC
• Remove Cypress PSoC 6 SoC and Devicetree

Concerns and Unresolved Questions

It is unclear how we should use source code generated from our ModusToolbox Configurators. These tools can be used to configure a device, including clock trees, peripheral settings (e.g. UART, PWM, ADC, etc.) and other system settings. We can include the generated code for our CY8CPROTO-062-4343W in our hal_infineon repository and then build our board-specific Kconfig files based on that code. Is that an acceptable means of doing this, or must all board-level configuration be done via Kconfig, with board-specific generated source disallowed?

Alternatives

As Alternatives to removing existing CY8CKIT-062-BLE and CY8CKIT-062-WIFI-BT board support, we can implement the
following migration plan:
1. Integrate new Infineon Hardware Abstraction Layer (HAL) implementation. Refer to tasks 1 through 9
2. Migrate CY8CKIT-062-BLE to new PSoC6 implementation
3. Migrate CY8CKIT-062-WIFI-BT to new PSoC6 implementation
4. Remove old PSoC6 SoC implementation