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drivers: sensor: lsm6dso: add support for tilt and tap triggers #89205
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drivers: sensor: lsm6dso: add support for tilt and tap triggers #89205
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Tilt or Tap can be selected via config and further tap parameters can be configured via DT. Signed-off-by: Ivan Wagner <[email protected]>
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Anyone willing to take a look a this? |
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@avisconti can you take a look?
@ivanwagner can you take a look at the recent comments? Thanks! |
I will make changes and test it next week and push everything so you can have a look. Thank you |
Improvements include: check error codes, log level adjustments, removed unreachable code, disable tilt when not used, call optimized interrupt handler when tilt and tap are not used. Signed-off-by: Ivan Wagner <[email protected]>
@@ -206,10 +516,11 @@ static void lsm6dso_handle_interrupt(const struct device *dev) | |||
#endif | |||
} | |||
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gpio_pin_interrupt_configure_dt(&cfg->gpio_drdy, | |||
GPIO_INT_EDGE_TO_ACTIVE); | |||
gpio_pin_interrupt_configure_dt(&cfg->gpio_drdy, GPIO_INT_EDGE_TO_ACTIVE); |
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Generally you don't want to turn on/off the edge triggers. This is outside of the scope of this PR, but I recommend revisiting this for this driver. On level interrupts you want to turn it off because it'll keep firing until you read the status register. With edge interrupts it's safe to leave it on this way you're not missing events.
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Look almost good. Just small nits
Added comments ad the end of preprocessor if else endif blocks Signed-off-by: Ivan Wagner <[email protected]>
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Please retry analysis of this Pull-Request directly on SonarQube Cloud |
This patch adds support for tilt, tap and double tap triggers. As an example ST IIS2DLPC sensor was taken as an example. In fact DT new properties are taken from there with the same philosophy.
A new sensor trigger value has been added: SENSOR_TRIG_TILT
When the interrupt handler is called, access to 5 registers will determine information regarding any interrupt flag available on this devices. This adds extensibility for future features at a cost of accessing 5 registers.