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When writes are issued to the mram controller without verifying that it is ready, it can cause the reads to be stalled until all writes finish. Fix this by adding a wait busy loop before any MRAM_WORD aligned write.

LOG_DBG("write: %p:%zu", (void *)addr, len);

memcpy((void *)addr, data, len);
for (uint32_t i = 0; i < (len / MRAM_WORD_SIZE); i++) {
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static inline to avoid duplication

#define ERASE_VALUE 0xff

#define SOC_NRF_MRAMC_ADDR DT_REG_ADDR(DT_PARENT(DT_DRV_INST(0)))
#define SOC_NRF_MRAMC_READY_REG (MRAM_START + 0x400)
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@rghaddab rghaddab force-pushed the rghaddab/mram-wait-ready branch 2 times, most recently from cbb9e28 to c88ab19 Compare October 16, 2025 13:25
When writes are issued to the mram controller without verifying that it
is ready, it can cause the reads to be stalled until all writes finish.
Fix this by adding a wait busy loop after each MRAM_WORD aligned write.

Signed-off-by: Riadh Ghaddab <[email protected]>
@rghaddab rghaddab force-pushed the rghaddab/mram-wait-ready branch from c88ab19 to 562b993 Compare October 16, 2025 14:08
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3 participants