Four channel voltage monitor — hardware design
This article goes through the hardware design procedure for the four channel voltage monitor along with the simulation results.
Design of voltage level shifter
The voltage level shifter has to translate a common mode voltage of -40V to 40V to an output voltage of 0.3V to 3V respectively. The circuit must have a bandwidth of atmost 1 khZ and an input impedane of atleast 100 kΩ.
The design equations are obtained from the following Medium article:
The voltage level shifter has the following circuit diagram:
The attenuation factor of the circuit is given by
The bias voltage is chosen to be 3.3V and the bias resistor R_Bis chosen as 10kΩ.
The bias factor B is calculated as follows
The input side resistance R_1 and the attenuation resistance R_2 is calculated as follows
The input impedance is given by
which above 100 kΩ. The required capacitance is
Choose a filter capacitance of 100nF.
Get Patrick A Joseph’s stories in your inbox
Join Medium for free to get updates from this writer.
Using the Okawa electric design tool (Optimum Resistors Find Tools) the following values are selected for R_1 and R_2
Simulation results
DC simulation
The input common voltage is varied from -40V to 40V and the output voltage is observed.
From the simulation, it can be seen that the at input voltage of -20V, the output voltage is 994.71mV and at 20V, the output voltage is 2.35V.
The slope is given by
The bias is calculate using the slope-intercept equation as follows
AC simulation
The frequency of the input signal is varied from 1Hz to 1KHZ and the Bode plot (magnitude and phase response) is plotted.
It can be seen that the corner frequency for the filter is at 313.71Hz.
