Sktbttr·Oct 27Debugging Setup Timing Degradation from Placement to Post-CTS: A Practical Physical Design Case…Author: Shaik Thouheed Email: sktbttr@gmail.com
Sktbttr·Oct 18Beyond Physical Design: My Journey Toward Becoming a VLSI Solution ArchitectAuthor: Shaik Thouheed Email : sktbttr@gmail.com
VLSI Physical design Hub·Jun 12Signal Integrity Analysis (1)Two parallel signal wires exhibit coupling capacitance between them. Therefore, when one signal switches, it can affect the neighboring net…
Rana Umar Nadeem·Jun 5Design for Testability: MISR Deep Dive The Mathematics of CompactionThe previous article introduced the MISR as the hardware mechanism that compresses a long response stream into a short final signature. The…
Rana Umar Nadeem·Jun 3Design for Testability: Response Compaction and Signature AnalysisThe previous article closed with the decompressor: a network that takes a small number of external inputs and expands them into a much…
Rana Umar Nadeem·May 29Design for Testability: Scan Chain Balancing and Physical-Aware StitchingScan gave us access, but access itself has now become expensive.
Agnathavasi·Dec 23, 2025SDC – The Commands That Define Timing in Physical DesignHello folks 👋, welcome to Day 4 of my 100 Days of Physical Design journey.
Ahmed Abdelazeem·Dec 21, 2025No-Change Timing Arcs vs. set_data_checkWhy Stability Checks Are Not Data Checks (and What Breaks in Silicon)
VLSIPD·May 13, 2025Filler Cells in VLSI Physical DesignIn physical design, most engineers focus on cells that do something — logic gates, buffers, flip-flops. But there’s another category of…
Srinivas Rahul Sapireddy·Aug 11, 2024Exploring Logic Synthesis with Yosys: A Tutorial OverviewIn the evolving world of VLSI design, the journey from RTL (Register-Transfer Level) to GDS (Graphic Data System) is both intricate and…A response icon1A response icon1
