Sktbttr·Oct 27Debugging Setup Timing Degradation from Placement to Post-CTS: A Practical Physical Design Case…Author: Shaik Thouheed Email: sktbttr@gmail.com
Sktbttr·Oct 18Beyond Physical Design: My Journey Toward Becoming a VLSI Solution ArchitectAuthor: Shaik Thouheed Email : sktbttr@gmail.com
VLSI Physical design Hub·Jun 12Signal Integrity Analysis (1)Two parallel signal wires exhibit coupling capacitance between them. Therefore, when one signal switches, it can affect the neighboring net…
Rana Umar Nadeem·Jun 5Design for Testability: MISR Deep Dive The Mathematics of CompactionThe previous article introduced the MISR as the hardware mechanism that compresses a long response stream into a short final signature. The…
Rana Umar Nadeem·Jun 3Design for Testability: Response Compaction and Signature AnalysisThe previous article closed with the decompressor: a network that takes a small number of external inputs and expands them into a much…
