InTowards AIbySrinivas kodali·5d agoPCIe in AI Inference: Where It Shines and Where It LagsNov 7, 2026 · @Srinivas Kodali
Joshi Sumit·Oct 14Building AI Accelerators: Infrastructure, Compilers, and HW-SW Co-Design — Part 1A: PCIe Hardware…DMA as a Distributed System
Abdulrahman Maslmany·Oct 12PCIe 4.0 x8/x8 vs x16/x16 for Dual GPUs: Does Bandwidth Choke Local LLM Tensor Parallelism?An engineering audit on bus bifurcation, NCCL AllReduce synchronization bubbles, and 70B token generation velocity.
Om Narasimhan·Aug 21A deep dive into PERST# — The Signal That Decides Whether Your PCIe Link Ever TrainsMost PCIe bring-up debug efforts eventually trace back to one net: PERST#. Beginners take it as an unassuming active-low signal that is…
Abhishekojha·Aug 8Building a QEMU PCIe Device from ScratchBuilding a PCIe Device from Scratch Inside QEMU
Noah Bean·May 4The Signal Is Always Wrong NowHow PCI Express stopped trying to fix the channel and redesigned everything around the assumption that it’s broken.
Tom Herbert·Jan 19Memory Addressing and Memory Mapped I/OWe take a look at memory addressing and Memory Mapped I/O.A response icon2A response icon2
Allenyllee·Nov 21, 2025發現一個 linux kernel 無法根據 BIOS ACPI 設定正確關閉 ASPM 的 bug從 ACPI spec 查到 PCIe ASPM Control bit，它是在 FACP table 下的 IAPC_BOOT_ARCH flag:
Mr.PlanB·Sep 17, 2025ZFS and Uneven PCIe Lanes: What Really Happens When You Mix Fast and Slow DrivesIt starts with a simple plan: take two shiny Samsung 990 Pro SSDs and set them up in a striped pool. On paper, that sounds like storage…
Guides Arena·Dec 11, 2024Advantages Of PCIE 4.0Modern computers’ backbone is the PCI Express (PCIe) interface, which lets the CPU interact with other parts such graphics cards, storage…
