The Python core development team has announced that the open instruction set architecture RISC-V is now officially supported by CPython as a Tier 3 platform. The announcement was shared on the Python Insider blog by contributor Stan Ulbrych, following sustained efforts across the community to stabilise and validate the implementation on real silicon.
Reaching official inclusion in PEP 11, Python’s platform support document, required extensive collaborative work. Contributors spent months running tests on real physical hardware, resolving architecture-specific bugs, strengthening the build infrastructure, submitting patches, and reviewing changes. Ulbrych specifically highlighted hardware backing from the RISE Project, which provided multiple physical RISC-V machines to serve as buildbots for running automated tests and debugging architecture-specific problems.
While Tier 3 designation marks a critical step forward, significant development remains underway. Buildbots typically execute tests only after a patch lands, which introduces latency when identifying defects. To address this, the team is working with the RISE Project through their RISE RISC-V Runners initiative to introduce RISC-V hardware directly into CPython’s continuous integration pipeline, offering contributors faster automated feedback.
Looking further ahead, maintainers plan to advance RISC-V toward Tier 2 support within PEP 11. Core contributors also aim to investigate architecture-specific optimisations that unlock higher runtime performance by taking better advantage of RISC-V platform capabilities.
To validate stability across diverse setups, the development team has issued an explicit call for testing from developers with access to compatible boards. Ulbrych noted: "Importantly, we need people to use it and give us feedback. If you have access to RISC-V hardware, please try building and running CPython, run your workloads and test suites, and please let us know what breaks."
Finally, Ulbrych emphasised that CPython represents only a single layer of the broader ecosystem. Expanding full RISC-V viability will rely on ongoing community contributions across third-party Python packages, compilers, toolchains, and developer infrastructure.
Community discussions on Hacker News and Reddit’s RISCV community welcomed the milestone as a vital maturity signal, while actively dissecting the practical engineering implications of a Tier 3 designation. Developers noted that while Tier 3 status means the platform can still occasionally experience breakage without blocking core releases, official upstream support removes a major historical friction point for integrating RISC-V into software CI/CD pipelines. Conversations also centred around hardware profiles like RV64GC and upcoming standards like RVA23, exploring how modern core capabilities, such as vector extensions, bit manipulation, and branchless instructions, could eventually be leveraged to optimise Python interpreter performance.
RISC-V represents an open-standard instruction set architecture designed to provide an alternative to proprietary counterparts like x86 and ARM. Unlike x86, which is proprietary and closely guarded by legacy commercial entities, or ARM, which operates under restrictive licensing fees and strict corporate control, RISC-V is developed as an open standard that anyone can implement. Because its specification is fully accessible and modular, the surrounding ecosystem has expanded considerably in recent years, with industry projections estimating it will quadruple by 2032. This openness eliminates vendor lock-in, avoids proprietary licensing barriers, and provides a customizable, royalty-free hardware foundation for modern computing. Ensuring Python operates reliably across these systems has consequently become a major priority for the language ecosystem.